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MK32VT1664A-8YC (98.07.17) page 1/11 semiconductor MK32VT1664A-8YC 16,777,216 word x 64 bit synchronous dynamic ram module (2bank): description the oki MK32VT1664A-8YC is a fully decoded, 16,777,216 x 64bit synchronous dynamic random access memory composed of sixteen 64mb drams (8mx8) in tsop packages mounted with decoupling capacitors on a 168-pin glass epoxy dual-in-line package supports any application where high density and large capacity of storage memory are required, like for example pcs or servers. features 16-meg word x 64-bit (2bank 8byte) organization 168-pin dual inline memory module all dq pins have 10 w damping resister single 3.3v power supply, 0.3v tolerance input :lvttl compatible output :lvttl compatible refresh : 4,096 cycles/64 ms programmable data transfer mode ? /cas latency (2, 3) ? burst length (1, 2, 4, 8, full) ? data scramble (sequential, interleave) /cas before /ras auto-refresh, self-refresh capab ility serial presence detect (spd) with eeprom product organization operation access time (max.) product name frequency (max.) t ac2 t ac3 MK32VT1664A-8YC 125 mhz 10.0ns 6.0ns note. specification are subject to change without notice.
MK32VT1664A-8YC (98.07.17) page 2/11 block diagram / cs0 cke0 dqmb0 dqmb1 dq0 dq7 dq0 dq7 dq8 dq15 dqmb4 dq0 dq7 dqm cke / cs dqm cke / cs dq40 dq47 dqmb5 dqmb2 dqmb3 dq0 dq7 dq16 dq23 dq0 dq7 dq24 dq31 dqmb7 dq0 dq7 dq48 dq55 dq0 dq7 dq56 dq63 dqm cke / cs dqm cke / cs dqm cke / cs dqm cke / cs / cs2 dqmb6 dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs / cs1 / cs3 cke1 dq32 dq39 dq0 dq7 dqm cke / cs dq0 dq7 dqm cke / cs 10k w vcc vss two decoupling capacitors per sdram 0.1uf 0.33uf / ras,/cas,/we a0-a11,ba0,ba1 116 scl sda a0 a1 a2 sa0 sa1 sa2 serial pd clk2 3.3pf 5 6 clk0 1 2 clk3 3.3pf clk1 10 11 14 15 7 8 3 412 13 16 wp 47k w 9 6 10 3 4 911 12 15 16 13 14 1 8 7 2 17 5 3.3pf 3.3pf note. the value of all resistors is 10 w expect wp and cke1 module outline (front) (back) 1 85 10 94 11 95 40 124 41 125 84 168
MK32VT1664A-8YC (98.07.17) page 3/11 pin configuration fr o nt b ac k s i de fr o nt s i de b ac k s i de pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vss 85 vss 43 vss 127 vss 2 dq0 86 dq32 44 n.c 128 cke0 3 dq1 87 dq33 45 /cs2 129 /cs3 4 dq2 88 dq34 46 dqmb2 130 dqmb6 5 dq3 89 dq35 47 dqmb3 131 dqmb7 6 vcc 90 vcc 48 n.c 132 n.c 7 dq4 91 dq36 49 vcc 133 vcc 8 dq5 92 dq37 50 n.c 134 n.c 9 dq6 93 dq38 51 n.c 135 n.c 10 dq7 94 dq39 52 n.c 136 n.c 11 dq8 95 dq40 53 n.c 137 n.c 12 vss 96 vss 54 vss 138 vss 13 dq9 97 dq41 55 dq16 139 dq48 14 dq10 98 dq42 56 dq17 140 dq49 15 dq11 99 dq43 57 dq18 141 dq50 16 dq12 100 dq44 58 dq19 142 dq51 17 dq13 101 dq45 59 vcc 143 vcc 18 vcc 102 vcc 60 dq20 144 dq52 19 dq14 103 dq46 61 n.c 145 n.c 20 dq15 104 dq47 62 n.c 146 n.c 21 n.c 105 n.c 63 cke1 147 n.c 22 n.c 106 n.c 64 vss 148 vss 23 vss 107 vss 65 dq21 149 dq53 24 n.c 108 n.c 66 dq22 150 dq54 25 n.c 109 n.c 67 dq23 151 dq55 26 vcc 110 vcc 68 vss 152 vss 27 /we 111 /cas 69 dq24 153 dq56 28 dqmb0 112 dqmb4 70 dq25 154 dq57 29 dqmb1 113 dqmb5 71 dq26 155 dq58 30 /cs0 114 /cs1 72 dq27 156 dq59 31 n.c 115 /ras 73 vcc 157 vcc 32 vss 116 vss 74 dq28 158 dq60 33 a0 117 a1 75 dq29 159 dq61 34 a2 118 a3 76 dq30 160 dq62 35 a4 119 a5 77 dq31 161 dq63 36 a6 120 a7 78 vss 162 vss 37 a8 121 a9 79 clk2 163 clk3 38 a10 122 ba0 80 n.c 164 n.c 39 ba1 123 a11 81 wp 165 sa0 40 vcc 124 vcc 82 sda 166 sa1 41 vcc 125 clk1 83 scl 167 sa2 42 clk0 126 n.c 84 vcc 168 vcc pin name function pin name function vcc power suppl y ( 3.3v ) /we write enable vss ground ( 0v ) dqmb# data input/output mask clk# s y stem clock dq# data input/output /cs# chip select wp write protect cke# clock enable sda data i/o for spd a0-a11 address scl clk input for spd ba0 , ba1 bank select address sa# socket position address for spd /ras row address strobe n.c no connection /cas column address strobe
MK32VT1664A-8YC (98.07.17) page 4/11 serial presence detect byte no. spd hex value remark notes 0 80 defines the number of bytes written into spd memory 128 byte 1 08 total number of bytes of spd memory 256 byte 2 04 fundamental memory type sdram 3 0c number of rows 12 rows 4 09 number of columns 9 columns 5 02 number of module banks 2 bank 6 40 data width of this assembly 64 bits 7 00 ... data width conti nuation 0 8 01 voltage interface level lvttl 9 80 cycle time (cl=3) cl=3 t cc =8ns 10 60 access time from clk (cl=3) cl=3 t ac3 =6ns 11 00 dimm configuration type none parity 12 80 refresh rate / type normal / self 13 08 primary sdram width x8 14 00 error checking sdram width 15 01 minimum clk delay t ccd : 1 clk 16 8f burst lengths supported 1, 2, 4, 8, f 17 04 number of banks on each sdram 4 banks 18 06 /cas latency 2, 3 19 01 /cs latency 0 20 01 /we latency 0 21 00 sdram module attributes 22 0e sdram device attributes : general 23 c0 cycle time (cl=2) cl=2 t cc2 =12ns 24 a0 access time from clk (cl=2) cl=2 t ac2 =10ns 25 00 cycle time (cl=1) not support 26 00 access time from clk (cl=1) not support 27 1e minimum row pulse width t rp =30ns 28 10 /ras to /ras bank delay t rrd =16ns 29 14 /ras to /cas delay t rcd =20ns 30 30 minimum /ras precharge time t ras =48ns 31 10 density of each bank on module 64mb 32 20 command and address signal input setup time 2ns 33 10 command and address signal input hold time 1ns 34 20 data signal input setup time 2ns 35 10 data signal input hold time 1ns 36-61 00-00 r.f.u 62 12 spd data revision code 1.2 63 4a checksum for byte 0-62 64-71 41, 45, 20, 20, 20, 20, 20, 20 manufacturers jedec id code 72 01/06 manufacturing location 73-90 4d, 4b, 33, 32, 56, 54, 31, 36, 36, 34 , 41 , 2d , 38 , 59 , 43 , 20 , 20 , 20 manufacturers part number mk32vt1664a- 8yc 91,92 20,20 revision code 93-125 00-00 r.f.u 126 64 intel specification frequency 100mhz 127 f5 intel specification /cas latency clk0-3, cl=3 128-255 ff-ff unused storage locations
MK32VT1664A-8YC (98.07.17) page 5/11 electrical characteristics absolute maximum ratings rating symbol value unit voltage on any pin relative to vss v in , v out -0.5 to vcc+0.5 v vcc supply voltage vcc, vccq -0.5 to 4.6 v storage temperature t stg - 55 to 125 c power dissipation p d * 16 w short circuit current i os 50 ma operating temperature t opr 0 to 70 c *: ta=25 c recommended operating conditions (voltages referenced to vss = 0v) parameter symbol min. typ. max. unit power supply voltage v cc, v cc q 3.0 3.3 3.6 v input high voltage v ih 2.0 - vcc+0.3 v input low voltage v il -0.3 - 0.8 v capacitance (vcc = 3.3v 0.3v,ta = 25c f =1mhz) parameter symbol max. unit input capacitance(a0-a11,ba0,ba1,/ras, /cas,/we) c in1 98 pf input capacitance(/cs0,/cs1,/cs2,/cs3) c in2 34 pf input capacitance(dqmb0-dqmb7) c in3 22 pf input capacitance(cke0,cke1) c in4 58 pf i/o c apacitance(dq0-dq63) c i/o 25 pf input capacitance(clk0,clk1,clk2,clk3) c clk 50 pf
MK32VT1664A-8YC (98.07.17) page 6/11 dc characteristics (vcc = 3.3v 0.3v, ta = 0 to 70c) condition module spec. parameter symbo l cke others min. max. unit note output high voltage v oh - i oh = -2.0ma 2.4 -v output low voltage v ol - i ol = 2.0ma -0.4v input leakage current i li - - -80 80 ua output leakage current i lo - - -10 10 ua average power supply current (operating) i cc 1 cke 3 v ih t cc =min. t rc =min. no burst - 1240 ma 1, 2 power supply current (stand by) i cc 2 cke 3 v ih t cc =min. - 480 ma 3 average power supply current (clock suspension) i cc 3s cke v il t cc =min. -96ma 2 average power supply current (active stand by) i cc 3 cke 3 v ih , /cs 3 v ih t cc =min. - 720 ma 3 power supply current (burst) i cc 4 cke 3 v ih t cc =min. - 1560 ma 1, 2 power supply current (auto-refresh) i cc 5 cke 3 v ih t cc =min. t rc =min. - 1720 ma 2 average power supply current (self-refresh) i cc 6 cke 0.2v t cc =min. -16ma average power supply current (power down) i cc 7 cke v il t cc =min. -32ma notes: 1. measured with the output open. 2. address and data can be changed once or not be changed during one cycle. 3. address and data can be changed once or not be changed during two cycle. mode set address keys write burst /cas latenc y burst t y pe burst len g th a9 write burst a6a5a4 cl a3 bt a2a1a0 bt=0 bt=1 0 burst write 0 0 0 reserved 0 se q uential 0 0 0 reserved reserved 1sin g le bit write 0 0 1 reserved 1 interleave 0 0 1 2 2 010 2 010 4 4 011 3 011 8 8 1 0 0 reserved 1 0 0 reserved reserved 1 0 1 reserved 1 0 1 reserved reserved 1 1 0 reserved 1 1 0 reserved reserved 1 1 1 reserved 1 1 1 full pa g e reserved note: a7,a8, a10,a11,ba0,ba1 and all should stay "l" during mode set cycle.
MK32VT1664A-8YC (98.07.17) page 7/11 power on sequence 1. with inputs in nop state, turn on the power supply and enter the system clock. 2. after the vcc voltage has reached the specified level, take a pause of 200us or more with the input being nop. 3. enter the precharge all bank command. 4. apply cbr auto-refresh eight or more times. 5. enter the mode register setting command.
MK32VT1664A-8YC (98.07.17) page 8/11 ac characteristic (vcc = 3.3v 0.3v, ta = 0 ~70c) note 1, 2 . parameter symbol m odule spec. unit note min. max. clock cycle time cl=3 t cc 8-ns cl=2 12 - ns access time from clock cl=3 t ac - 6 ns 3, 4 -10ns3, 4 clock "h" pulse time t ch 3-ns clock "l" pulse time t cl 3-ns input setup time t si 2-ns input hold time t hi 1-ns output low impedance time from clock t olz 3-ns output high impedance time from clock t ohz -8ns output hold from clock t oh 3-ns3 /ras cycle time t rc 80 - ns /ras precharge time t rp 30 - ns /ras active time t ras 48 100,000 ns /ras to /cas delay time t rcd 20 - ns write recovery time t wr 8-ns /ras to /ras bank active delay time t rrd 16 - ns refresh time t ref -64ms power-down exit set-up time t pde t si +1clk - ns input level transition time t t -3ns /cas to /cas delay time (min) i ccd 1 cycle clock disable time from cke i cke 1 cycle data output high impedance time from dqmb i doz 2 cycle data input mask time from dqmb i dod 0 cycle data input time from write command i dwd 0 cycle data output high inpedance cl=3 i roh 3 cycle time from precharge command cl=2 2 cycle active command input time from mode register set command input (min) i mrd 2 cycle write command input time from output t owd 2 cycle notes: 1) ac measurements assume t t =1ns. 2) the reference level for timing of input signals is 1.4v. 3) this parameter is measured with a load circuit equivalent to 1 ttl load and 50pf (r load is 50ohm). 4) an access time is measured at 1.4v. 5) if t t is longer than 1ns, the reference level for timing of input signals are v ih and v il . output 50pf output load 50 w 1.4v
MK32VT1664A-8YC (98.07.17) page 9/11 function truth table (table1)(1/2) current state /cs /ras /cas /we ba addr action idle h x x x x x nop lhhhxxnop l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra row active l l h l ba a10 nop 4 l l l h x x auto-refresh or self-refresh 5 l l l l l op code mode register write row active h x x x x x nop lhhxxxnop l h l h ba ca, a10 read l h l l ba ca, a10 write l l h h ba ra illegal 2 l l h l ba a10 precharge lllxxxillegal read h x x x x x nop(continue row active after burst ends) l h h h x x nop(continue row active after burst ends) l h h l ba x burst stop l h l h ba ca, a10 term burst,start new burst read 3 l h l l ba ca, a10 term burst,start new burst write 3 l l h h ba ra illegal 2 l l h l ba a10 term burst,execute row precharge lllxxxillegal write h x x x x x nop(continue row active after burst ends) l h h h x x nop(continue row active after burst ends) l h h l ba x burst stop l h l h ba ca, a10 term burst,start new burst read 3 l h l l ba ca, a10 term burst,start new burst write 3 l l h h ba ra illegal 2 l l h l ba a10 term burst,execute row precharge 3 lllxxxillegal read with h x x x x x nop(continue burst to end and enter row precharge) auto precharge l h h h x x nop(continue burst to end and enter row precharge) l h h l ba x illegal 2 l h l h ba ca, a10 illegal 2 l h l l x x illegal l l h x ba ra, a10 illegal 2 lllxxxillegal write with h x x x x x nop(continue burst to end and enter row precharge) auto precharge l h h h x x nop(continue burst to end and enter row precharge) l h h l ba x illegal 2 l h l h ba ca, a10 illegal 2 l h l l x x illegal l l h x ba ra, a10 illegal 2 lllxxxillegal
MK32VT1664A-8YC (98.07.17) page 10/11 function truth table (table1)(2/2) current state /cs /ras /cas /we ba addr action precharge h x x x x x nop ? idle after t rp lhhhxxnop ? idle after t rp l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 nop 4 lllxxxillegal write h x x x x x nop recovery l h h h x x nop l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 illegal 2 lllxxxillegal row active h x x x x x nop row active after t rcd l h h h x x nop row active after t rcd l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 illegal 2 lllxxxillegal refresh h x x x x x nop ? idle after t rc lhhxxxnop ? idle after t rc l h l x x x illegal l l h x x x illegal lllxxxillegal auto resister h x x x x x nop access l h h h x x nop l h h l x x illegal l h l x x x illegal l l x x x x illegal abbreviations ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge notes: 1. all inputs will be enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. satisfy the timing of t ccd and t wr to prevent bus contention. 4. nop to bank precharging or in idle state. precharges activated bank by ba or a10. 5. illegal if any bank is not idle.
MK32VT1664A-8YC (98.07.17) page 11/11 function truth table (cke) (table2) current state(n) cken-1 cken /cs /ras /cas /we addr action self refresh h x x x x x x invalid l h h x x x x exit self refresh ? abi l h l h h h x exit self refresh ? abi l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain self refresh) power down h x x x x x x invalid l h h x x x x exit power down ? abi l h l h h h x exit power down ? abi l h l h h l x illegal l h l h l x x illegal l h l x x x x illegal 6 l l x x x x x nop(continue power down mode) all banks idle 6 h h x x x x x refer to table 1 (abi) h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l h l x illegal h l l l l h x enter self refresh h l l l l l x illegal llxxxxxnop any state h h x x x x x refer to operations in table 1 other than h l x x x x x begin clock suspend next cycle listed above l h x x x x x enable clock of next cycle l l x x x x x continue clock suspension notes: 6. power-down and self refresh can be entered only when all the banks are in an idle state.

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